Modern computer systems typically include one or more buses for interconnecting system components and for communicating with one or more processors. For instance, many modern desktop and server computer systems utilize the Peripheral Component Interconnect (“PCI”) Bus Architecture Standard. Through the PCI buses in a computer system, communication can be made between devices, system memory, and the host processor(s).
Due to limitations on the number of devices that may be present on a single PCI bus imposed by the PCI Bus Architecture Standard, and for performance-related reasons, many computer systems utilize multiple PCI buses. Buses can be added to an existing bus using devices called PCI-to-PCI bridges (“PPBs,” “bridges,” or “bridge devices”). PPBs provide connectivity between a primary, or upstream bus, and a secondary, or downstream, bus. Many of today's desktop and server computer systems contain multiple PPBs and, therefore, may have many buses. For instance, several PPBs may be utilized on the system mainboard, and additional PPBs may be installed on add-on adapter cards.
In order to enable access to the devices connected to each bus in a computer system, each bus must be given a unique bus number. The firmware utilized in systems with PCI bus architectures numbers the buses present in a system at startup according to the PCI Bus Architecture Standard. Such firmware typically begins assigning PCI bus numbers starting from bus zero because the firmware is only aware of the existence of PCI bus zero, the first bus number detected on the primary PCI bus. The firmware detects any additional buses and allocates bus numbers to each PPB it detects during system initialization. By utilizing the bus numbers assigned by the firmware, the operating system executing on the computer can identify and communicate with all the devices within a system, including those located downstream of PPBs.
Some computing systems have multiple processor “sockets,” each of which corresponds to a central processing unit (“CPU” or “processor”) present in the computing system. Each socket can also have multiple root bridges. A root bridge connects a primary PCI bus (e.g. bus zero), to a secondary PCI bus (e.g. PCI bus one). In turn, each root bridge can have multiple devices connected to it, including multiple PPBs.
As one example, a computing system might have four processors with four root bridges per processor. In this configuration, resources such as bus numbers must be allocated to the buses coupled to 16 different root bridges. The number of available bus numbers is, however, commonly restricted to 256 in a single segment. The total number of available buses (e.g. 256) are also commonly pre-allocated equally to the root bridges in a computing system. In the example configuration above, for instance, each root bridge would be pre-allocated 16 buses. During enumeration, the bus numbers pre-allocated to a root bridge are assigned to devices coupled to that root bridge.
If the number of actual buses coupled to a root bridge exceeds the number of buses pre-allocated to that root bridge, then it will not be possible to assign resources to some of the bridge devices coupled to the root bridge. This would occur, for instance, in a configuration where 16 bus numbers are pre-allocated to a root bridge, but the root bridge is coupled to more than 16 buses. As a result, a bus out-of-resource (“OOR”) condition will occur, the bridge devices to which bus numbers could not be allocated will be unavailable, and the computing system might exhibit non-deterministic behavior.
It is with respect to these and other considerations that the disclosure made herein is presented.